Sync Preload operation Interrupt raw register
L1_ICACHE0_PLD_DONE_INT_RAW | The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is done. |
L1_ICACHE1_PLD_DONE_INT_RAW | The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is done. |
L1_ICACHE2_PLD_DONE_INT_RAW | Reserved |
L1_ICACHE3_PLD_DONE_INT_RAW | Reserved |
L1_CACHE_PLD_DONE_INT_RAW | The raw bit of the interrupt that occurs only when L1-Cache preload-operation is done. |
CACHE_SYNC_DONE_INT_RAW | The raw bit of the interrupt that occurs only when Cache sync-operation is done. |
L1_ICACHE0_PLD_ERR_INT_RAW | The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation error occurs. |
L1_ICACHE1_PLD_ERR_INT_RAW | The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation error occurs. |
L1_ICACHE2_PLD_ERR_INT_RAW | Reserved |
L1_ICACHE3_PLD_ERR_INT_RAW | Reserved |
L1_CACHE_PLD_ERR_INT_RAW | The raw bit of the interrupt that occurs only when L1-Cache preload-operation error occurs. |
CACHE_SYNC_ERR_INT_RAW | The raw bit of the interrupt that occurs only when Cache sync-operation error occurs. |